ASIC physical design engineer with a 2,5 years’ professional experience in the different steps of the IC design flow, mainly in the backend. Where my responsibilities included:
Design for testing (DfT) flow where I was focused on implementing a combination of the ATPG compression and Logic Built-in-Self test (LBIST), also generating serial and parallel patterns.
Physical Design Flow, where I’ve worked with adavanced node going from 65 to 12nm, my responsibilities starts from synthesis with scan insertion, LEC, floor-planning, place & route, and timing/DRC/LVS signoff.
I can describe myself as a fast learner, with a strong ability to develop, improve and adapt new and/or existing flows. I am a proactive person, who’s always up for new challenges.
particulier.
