ASIC physical design engineer with a 2,5 years’ professional experience in the different steps of the IC design flow, mainly in the backend. Where my responsibilities included:
Design for testing (DfT) flow where I was focused on implementing a combination of the ATPG compression and Logic Built-in-Self test (LBIST), also generating serial and parallel patterns.
Physical Design Flow, where I’ve worked with adavanced node going from 65 to 12nm, my responsibilities starts from synthesis with scan insertion, LEC, floor-planning, place & route, and timing/DRC/LVS signoff.
I can describe myself as a fast learner, with a strong ability to develop, improve and adapt new and/or existing flows. I am a proactive person, who’s always up for new challenges.
particulier.
Familiar with IC design methodology and state-of-art design tools
Implementation of algorithms to analyze the power consumption in Physical Design, particularly in the placement stage
Optimizing 11.7% of the dynamic power consumption on nets
Description de l'entreprise
Mentor Graphics helps engineers overcome increasingly complex challenges in the design of electronic systems.
The company's products are designed to make design engineers more productive, improve the accuracy of complex models and shrink "Time to Market". It provides software and hardware design solutions that enable businesses to develop electronic products quickly and efficiently.
