Maxim Verbitskiy

Resume created on DoYouBuzz

Experiences

Design verification with UVM (SystemVerilog) - PCIe (Gen3, Gen4) block level verification, APB periferals block level verification, design-specific subblocks verification
VCS simulator

Company Description

R&D center of SKHynix in Belarus

Company website

http://softeqflash.by/

FPGA design (RTL design, functional simulation) - mostly with Intel (Altera) FPGA's, minor expirience with Xilinx FPGA's
DSP algorithms implementation and testing (with Matlab, in FPGA's)
Analog and digital circuits design (Altium Designer)
Digital circuits testing with measurment equipment
C/C++ programming (API creation for QNX RTOS, Drivers development for Windows with Jungo WinDriver)

Company website

http://kbradar.by/en/

FPGA designer/ Design Verificator