Manjunath s
ManjuS VLSI Design Engineer
Cadence Virtuoso
Verilog/VHDL
VLSI / Embedded
ARM
Microcontrollers
33 years old
India
Employed
Available
INTERN
Reinfold Physical Innovation Labs, Bangalore.
September 2015
to February 2016
India
- PIC
ARM
ORCAD
INTERN
Hindalco Industries Limited Belgaum
August 2015
Belgaum
India
- Undergone In-Plant Training in Electrical and Instrumentation Department
Mtech in VLSI Design & Embedded Systems
Visvesvaraya Technological University PG Studies,Macche
September 2014
to August 2016
Pursuing Mtech in 4th semester VLSI Design & ES
(till 3st semester) (72.91%)
Grade – First Class with Distinction
(till 3st semester) (72.91%)
Grade – First Class with Distinction
B.E in Electronics & Communication Engineering
Gogte Institute Of Technology, Belgaum
July 2011
to May 2014
Visvesvaraya Technological University Belgaum
(May -2014) (67.24%)
Grade - First Class
(May -2014) (67.24%)
Grade - First Class
Diploma in Electronics & Communication Engineering
R.N.Shetty Polytechnic, Belgaum
May 2008
to May 2011
Department of Technical Education, Bangalore
(May -2011) (77.16 %)
Grade – First Class with Distinction
(May -2011) (77.16 %)
Grade – First Class with Distinction
Department of Pre-University Education , Bangalore
(July - 2008)
Grade - Pass
(July - 2008)
Grade - Pass
Karnataka Secondary Education Examination Board
(June - 2006) (64.48%)
Grade – First Class
(June - 2006) (64.48%)
Grade – First Class
-
IEEE GIT student branch
Coordinator for the state level event IGreen-2013. Organized events: Paanchajanya-14
-
COORDINATOR
Organized and coordinated for ”ROBOTICS“ event held at Gogte institute of technology, Belgaum.
-
VOLUNTEER
IEEE GIT Student Branch conducted event “PAANCHAJANYA 13”.A National Level Tech Fest Worked as Volunteer for RoboRash and Rush Lane.
- Qualified GRADUATE APTITUDE TEST IN ENGINEERING 2014(GATE) (2014).
-
Attended “NIIT 9 NATIONAL IT APTITUTE TEST 2013 ”conducted by NIIT, Belgaum
(2013). - Attended “GRADUATE EMPLOYABILITY TEST ”conducted by NIIT Belgaum (2012).
- Got first place in ”Science Exhibition ” conducted by Bharatesh Education Trust Belgaum (2005).
- Participated in the “La-Tex, a document preparation system for high – quality typesetting” held on 27th April 2015 at PG studies VTU-campus “Jnana Sangama”Belagavi
- Participated in Two days Training Program on “NuEdu-SDK-Nuc472 ARM Cortex M4” held from 21st to 22nd Nov 2014 Organized by Department of PG Studies, VLSI& ES, VTU, Belagavi.
- Participated in the “GOLD Interface 2013“ held at BEC-IEEE student Branch, Bagalkot conducted by IEEE Bangalore Section.
- Embedded Systems Workshop conducted by Spundhan Software Private Limited.
-
POWER LINE COMMUNICATION
Functional Objective: - We can use AC line as communication channel.
Description: Power line communications systems operate by adding a modulated carrier signal to the wiring system. Different types of power line communications use different frequency bands. Since the power distribution system was originally intended for transmission of AC power at typical frequencies of 50 or 60 Hz, power wire circuits have only a limited ability to carry higher frequencies. The propagation problem is a limiting factor for each type of power line communications. Higher data rates generally imply shorter ranges; a local area network operating at millions of bits per second may only cover one floor of an office building, but eliminates the need for installation of dedicated network cabling. -
ANALYSIS AND COMPARISON OF FILTERING TECHNIQUES FOR IMAGE RESTORATION
Project on: IMAGE PROCESSING (image restoration)
Type of project:- SOFTWARE
Description: The main objective of this project is to develop a prototype that restores an image from a given selected image, degraded with the noise using various filters. The peak to signal ratio is calculated for each type of filter implemented. The main goal of our project is to determine the best suited filter for removing a particular noise from the degraded image. -
DESIGN AND IMPLEMENTATION OF IP CORE FOR CAN PROTOCOL
Project: Front end Verilog HDL
Description: This projects gives a germane explanation for the Designing of CAN IP Core using Xilinx Design Suit 14.7 Verilog HDL, it follows the CAN protocol ISO 11898, half – duplex CSMA/CD+AMP and Implementation on FPGA using Spartan 3 XC3S200 as one node and Spartan 6 XC6SLX9 as another node.
-
A research paper titled "Analysis and Comparison of Filtering Techniques for Image
Restoration" was published in the Volume 2 Issue 01 Month Jan-Feb 2015 of International Journal of Multidisciplinary Approach and Studies (IJMAS). - A paper titled “Design and implementation of IP core for CAN PROTOCOL” was published in the volume 2, Issue 12, June 2016 of International journal of science Technology and Engineering (IJSTE).
- Undergone In-Plant Training in Electrical and Instrumentation Department at Hindalco Industries Limited Belgaum from 04-08-2015 to 28-08-2015.
- Completed six months of internship on “Designing And Testing A Tech-Knowledge B3 Development Board” at Reinfold Physical Innovation Labs, Bangalore.
- MATLAB, C, MULTISIM, Proteus
- Microcontroller 8051, MP 8086
- PIC Microcontroller
- ARM 7
- Verilog HDL,VHDL
- CADENCE VIRTUOSO , LEONARDO SPECTRUM
- Verilog HDL, VHDL
