Your browser is outdated!

To ensure you have the best experience and security possible, update your browser. Update now

×

Horace Sklar

Sr. Integration & Hardware Lead Aerospace Consultant

DO-254 DOORS MKS
I&T HW / FW Design VHDL
Technical Management
Subject Matter Expert
ridgidranch@alum.mit.edu hjsklar@gmail.com ridgidranch@alum.mit.edu 415.760.6213
304 Hatchery Ln95476 SonomaUnited States
Client Pre-Sales, DARPA SBIR proposal / Teami Phase 1/2 awards. Requirements capture (DOORS), analysis, flow-down, and traceability, architecture trade studies, definition, modeling. Hardware and firmware design and integration (IPT lead) governance per DO-178, DO-160, ARP4761 and rigorous aerospace developments involving design compliance and certification to RTCA/DO-254 Hardware Design Assurance for CEH ASIC and FPGAs. DO-254 work processes development such as FW Conceptual Design (HCD) using hierarchical VISIO diagrams that allocate and trace FW Requirement Specification (HRS) to Functional Blocks for subsequent FW Detail Design.

Embedded Systems / Hardware / ASIC / FPGA / Firmware design and development contract experience in Aerospace & Defense, Semiconductor, Computer, and Consumer industries. Technical Project engineering and system design experience in next-generation Fly-By-Wire (FBW) Flight Control Embedded Systems, Set-Top-Box, Space-based sensors integration: visible imaging spectrometer, medium / short wave infrared camera and detector focal plane subsystem with on-board processing subsystem, and Telecommunications equipment using digital broadband ELF, HF Kineplex, UHF wireless and wireline technologies with Secure Voice capability.
Resume created on DoYouBuzz
Education

EE , NON

Massachusetts Institute of Technology

September 1972 to June 1975
Electrical Engineering & Comp Science major in Communications. Dissertation titled “Cost-effective Automated Computerised Goldman Kinetic and Static Perimetry for Visual Field Testing" utilizing the Intel 4040 micropocessor, LED-based Static Display unit and polar-coordinate plotter. Focus on Stochastic Systems.

Activities and Societies: Research Assistant @ Draper Labs for "MARS Binocular Vision" project. Teaching Assistant for undergraduate Biology lab.

Bachelor of Science (BSEE)

Princeton University

September 1969 to June 1972
Electrical and Electronics Engineering program, BSEE-Magna Cum Laude. Qualified for Advanced Graduation in 3 years. Focus on Circuits & Systems.

Activities and Societies: Terrace Club, Table Tennis

Math Course Work

University of Miami

September 1968 to June 1969
Undergraduate level Mathematics program of seven classes from Calculus to Advanced Differential Equations and Riemann Surfaces for selected Math high school students offered (12 yrs old) through Center for Theoretical Studies. GPA 4.0.
Skills

SYSTEM & HARDWARE

  • FPGA Design: VHDL, Schematic, Models
    Good
  • DO-254, Design Assurance Guidance for Airborne Electronic Hardware
    Good
  • VHDL
    Good
  • Telelogic DOORS
    Good
  • ASIC LSI Logic
    Good
  • Embedded Systems
    Good
  • Hardware Architecture
    Advanced
  • Integrated Product Team Test
    Advanced
  • Xilinx, Actel, Lattice, Altera FPGA
    Good
  • Hardware Life Cycle
    Intermediate
  • Digital Signal Processing: Algorithms, ModelSim Simulation
    Advanced
  • Team Leadership: Technical
    Advanced
  • Signal Integrity
    Good
  • MKS Integrity Configuration Management
    Intermediate
  • Mentor DxDesigner Schematic Capture
    Advanced
  • System Architecture
    Advanced
  • Hardware Verification
    Advanced
  • Avionics Design
    Good
  • High Speed Design
    Good
  • Hardware Testing
    Advanced
  • Technical Staff Management
    Good
  • Modems
    Good
  • Satellite Hardware Design
    Good
  • Trade Studies
    Good
  • DSP
    Advanced
  • VME
    Good
  • cPCI
    Intermediate
  • Systems Engineering
    Good
  • Digital Image Processing
    Good
  • Timing Closure
    Good
  • Client Pre-Sales, SBIR Phase 1/2
    Advanced
  • Matlab
    Good

HDL

  • VHDL
    Good
  • Verilog
    Notions
  • TCL
    Intermediate
  • Python
    Notions

Languages

  • English
    Advanced
  • Spanish
    Advanced
  • French
    Intermediate
Experiences

Medical Leave

STL
2017 to 2020
  • Total Knee Replacement 2017 & 2019
  • 2013 - NOW: Renamed to Silicon Technology Labs LLC for Off-site Consulting, Contracting Services. Direct and agency submittals (1099, Corp-Corp). Clients include: Parker Aerospace, Northrop Grumman Corp. (NGC), B/E Aerospace.
  • 1998 - 2012: Silicon Technology Labs for consulting for Military, Avionics, and Commercial. Clients; Information Systems Labs (ISL), SAIC/EVSD, Phillips Labs, Catacaos Energy.
  • 1986 - 1998: Silicon Technology Labs formed as an SDB engineering services firm. 2500 sq.ft. facility in San Diego with 10 senior and mid-level engineers. SIC Code 3571, Cage Code 3DQ15, DUNS # 358090107. Seven DARPA SBIR Phase I & II, DoD, and commercial proposal wins. Over 30 San Diego, Southern California and Nationwide clients.
  • Client interface and negotiations. Proposal development, pre-sales interface. DARPA SBIR Phase 1 & Phase 2 wins.
  • FBW Electronic Backup Motor Control Electronics (EBMCE), Performing DO-254 compliant processes and design and development of complex firmware. DOORS Requirements analysis, MKS revision control. Authoring artifacts including plans, standards, checklists, requirements, reviews, configuration items, V&V results, troubleshooting, Problem Reports activities: Root-Cause Analysis, Resolution Verification.
  • BLDC Motor Control Law testing (PID Loops), Dead Band Compensation algorithm development, system integration, lab and ground testing.
  • Firmware VHDL code generation, Mentor QuantaSim Simulation for Xilinx/ISA and Lattice XP2 FPGA with Diamond/Reveal tools architecture, partitioning, VHDL code generation, integration and test.
  • IR&D Hyperspectral Imaging Spectrometer Spatial-Scanning "Push Broom" Demo for Remote Sensing using NASA EO-1, NGC built, Hyperion Instrument using"Band-In-Line" files. Spectral Binning Algorithm for simulating Landsat-7 Band Coefficients in real time using IEEE-754 standard floating-point arithmetic.
  • Memory efficient, Stream-Parallel Architecture and Firmware VHDL Development for Alpha Data XRM-ZBT
    COTS Board with Dual Xilinx Virtex-5 devices.
  • Subcontract via Technovare Systems Inc, Irvine, CA.
  • Design of high performance & reliability electronics for aircraft fly-by-wire (FBW) flight control systems. The Electric Backup Motor Control Electronics (EBMCE) LRU for Primary Flight Control Actuation System for family of business jet aircraft. Comprised of four circuit boards, the EBMCE interfaces to a brushless DC motor, system sensors, and electronic units. The EBMCE provides a backup position Control function that uses an FPGA to provide current loop closure for the motor control, receives motor velocity commands, executes over-voltage/current shutdown protection, and excites and demodulates a resolver attached to the motor shaft in order to sense motor position. The motor position is used to determine the sequence of phase current required to rotate the motor.
  • Developed HRS, HDD Requirements and traceability with Telelogic DOORS 9.0 in DO-254 airborne development process. Performed VHDL Firmware Design for Xilinx Spartan 3E/ISE 13.2 and Lattice XP2 Diamond Tool Suite. Mentor QuartaSim testbenches for unit test. I&T Plan development and verification executed in a Labview environment.
  • Advanced Boom Control Unit (ABCU) hardware/firmware verification and validation requiring FAA Supplemental Type Certificate, with Level B complex hardware FPGA, hardware bench tester. Requirements flowdown and traceability, IO12 & IO3 PWA re-design and verification test procedures (DVT) for circuit card test and system integration using LabVIEW™. SubVersion™ control and PADS™ schematic capture for analog (LVDT, Servo Motor Control, ADC/DAC circuits) and digital PWA. Supported PCB layout. Actel A3PE FPGA in VHDL embedded in a custom VME64x subsystem.
  • Providing design data and independent review verification in support of FAA certification.
  • Monetary award for exceptional contractor performance meeting critical delivery milestone.
  • Generated DVT for IO12, IO3 ABCU PWA on VME64x in LabVIEW™ automated test bench.
  • Navy Man-Portable Mine Detection.
  • Develop CAD methodology, train personnel, architecture development, design, cPCI COTS selection, integration, and hardware design of a 6U cPCI™ Data Acquisition Module. Design. 32-bit, 33Mhz PCI Bus-Master Interface with 9-channels DMA, Intel 21154 PCI-PCI Bridge, 8-channels 12-bit, 10Mhz Rx Data Acquisition with dithering, Dual 20 MHz Tx channels, dual Intersil 5216, and support of Xilinx Spartan-II FPGAs during I&T. DxDesigner EPD 2.0 tool suite, Xilinx ISE 4.2, PCI and FIFO IP cores.
  • Single, Tunable, 3-Frequency QR Probe Single Arbitrary Waveform Simulation Sequences 600 MFLOPS RFIM Processing Algorithm Robust CompactPCI® Architecture 19" Rack, 100W, 12" Depth, 12" Height DAS 66 MHz, 8-channel, Data Acquisition Module (DAM). Features > 100-dB SFDR/SNR Performance.
  • Ground Standoff Mine Detection System (GSTAMIDS) Block II design. . ISL's GSTAMIDS
  • Data Acquisition Subsystem (DAS) integrates ISL's RFIM technology with a next-generation QR spectrometer in a Linux-based CompactPCI® Architecture. 3 Frequency RFIM Antenna System
  • NFIRE satellite payload Lead Hardware design of VME64 Spacecraft Interface using ACT2 RadHard FPGA with MBLT/2eSST transfers, and VME64 Image Processor of target payload Electronics Control Module. DxDesigner with Actel Silicon Explorer II tools.
  • Delivered Portable Ground Based Simulator replacing Four 19” Racks of equipment
  • Develop Air Force Research Labs Portable MSTI-3 Payload Simulator. Architect and design of portable subsystem and board using two Actel ACT-3 FPGAs that accept three high speed video telemetry, command and control, sensors, housekeeping with a PCMCIA interface to laptop and three real-time B&W video outputs. DxDesigner and Actel CAE tools.
  • •Most reliable and successful satellite program in Phillips Labs.
  • •Edwards AFB I&T, Low Earth Orbit Launch in 1997, One Year Flawless.
  • Miniature Sensor Technology Insertion-3 (MSTI-3) Payload system architect/ designer for VME32 space-based payload Electronics Control Module consisting of design, simulation, test and integration of three fault-tolerant TMS320C30 camera and Spacecraft Interface PWA utilizing Actel ACT-2/3 FPGA and TI DSP processors. DxDesigner and ACT tools. Vacuum, temperature, acceptance testing at Edwards AFB.
  • • Led to DARPA Battlefield Neurocomputer SBIR & SNAP™4 1993.
  • • Led to SBIR Phase I CMP win & ViP daughterboard architecture
  • • Study to identify future architectures of neural net products.
  • Technology Lead for HNC Inc. and evaluation of alternate MIMD and SIMD massively-parallel neural-net architectures and trade-offs leading to SBIR awardswins. Technology assessments included custom ASIC, FPGA, and DSP based architectures.
  • HNC Inc., San Diego, CA | Crunch-860 Product Development
  • Contractor, Design Engineering
  • •SNAP won 1993 IEEE Gordon Bell Award for Price/Performance ,
  • •SNAP made of 4 NAP chips and memory for 4 GBPS IO & 640 MFLOPS
  • DARPA proposal team win resulting in system specification of a SIMD Army Battlefield Neurocomputer and resulting Numerical Array Processor ASIC consisting of a 1-D systolic array of 4 arithmetic cells in a SIMD ring and SNAP™ board level design of a 6.5 GFLOP floating-point processor. A 17-bit address bus allows maximum of 522 KB of memory per cell. LSI Logic ASIC project management and co-design of 300K gate density ASIC.
  • Warfighter Program CUE FPGA design, I&T and doc package release
  • Design Xilinx 4010 CUE™ FPGA for Air Force Warfighter Mil Parameter Encoder application, 25 MHz controller with 12K gate density using DxDesigner and Xilinx ICE tools. Performance of 25 MHz required custom floor planning and placement of individual critical path cells at Xilinx Main office site in Milpitas.
  • Fully simulated both ASICs and board level, used VHDL behavioral and VHDL RTL for improved simulation speed.
  • Developed new 4-stage pipelined MultiplierAccumulators (MAC).
  • Vision Image co-Processor (ViP™) Crunch-860 daughterboard consisting of a ViPIO (80K) ASIC and ViP (110K) ASIC, LSI Logic 100K foundry. Managed six ASIC engineers developing hierarchical VHDL designs with DxDesigner for chip, board level simulations and test benches, and LSIL MDE tools for timing, placement and verification. ViP ASIC resulted from an SBIR phase one patented 2D, 8x8 processing element systolic array architecture operating in lock-step at 30 Mhz. ViPIO provided dual-bank DRAM address generation and pre-fetching, Intel 860 handshaking, and local storage with data descrambling and formatting for the ViP ASIC.
  • Program management of 20 ASIC engineers in UNIX CAE environment.
  • System Administrator and VHDL benchmark support for three LSI Logic 300K technology ASICs, perform verification VHDL test benches and backend release process simulation, ATP, floor planning and production test vector for ATF program.
  • Vision Image Processor (ViP) daughterboard (ASIC based) for real-time Image Processing (1992)
  • Two 1st Pass Silicon LSI Logic ASICs (100K) for ViP PWA
  • DT-Connect Frame Buffer & Interface PWA daughterboard (1991)
  • 48MB, no wait state, pipelined Image Memory, 1st Pass PWA daughterboard (1991)
  • >1100 Crunch-860 sold on royalty resulting in > $2M profits
  • On schedule deliverey dual platform Crunch-860 PWA boards (1990)
  • STL Team of PM, four engineers and three contractors
  • Partially funded through SBIR Phase1/2 awards, royalty agreements, and contracts with HNC Inc.
  • Internal product development program of multi-phased, dual platform (PC/Windows & VME/UNIX) Intel i860-XP, 50MHz, 64-bit, VLIW ISA based Real Time Image Processor Workstation. Two custom Daughter boards slots provided targetted performance, memory and/or I/O interfaces. Developed requirements, architecture, and hardware design, prototype I&T. Worked with local manufacturing houses for PCB, PWA kit, assembly, and manufacturing test.
  • Cisco acquired Scientific-Atlanta in 2005 for $6.9B.
  • Architecture reduced LRUs from 12 down to a single PWA, 8-stage, loosely-coupled array of identical DSPs partitioned along data rate requirements via high speed serial IO. System design and performance using Matlab™ allowed for incremental and independent debugging of system, software, and hardware from remote sites. Design firmware code and test on FTAS real-time AT&T 32C™ DSP serial systolic architecture for ASW acoustic DSP narrowband algorithms. VME test bed with PC-based tools: Debugger, Simulator, Assembler. Used MATLAB and RTW for algorithm. Develop, produce 22 FTAS SCSI-2 Disk Array Units utilizing quad 1.6GB disk arrays in a 19" rack.
  • Innovative Linear Systolic DSP Architecture  Contract Win.
  • Validated Real Time “Hardware In The Loop” Development Methodology using an agile hardware development cycle.
  • Reduced LRUs from 8 to 1, minimizing life cycle costs and NRE.
  • Released 22 FTAS systems (FQX-3) and DAS chassis on schedule.
  • Proposal lead systems engineer for a 32-channel Fast Time Analyzer System (ASW), win based on innovative architecture. Efforts included signal processing algorithm development such as FFT and Polyphase Filters with Matlab™ Simulink and Hardware-in-the-Loop support, architecture trades with various DSPs (320C30, 56000, and 29000), application specific devices, coding, and system development concepts.
  • Lead system engineering for HNC Inc. and evaluation of alternate MIMD and SIMD massively-parallel neural-net architectures and trade-offs leading to SBIR awards and DARPA contract wins. Architecture study addresses the range from fully hard-wired physical neural nets to virtual machines using numerous neural net paradigms. Technology assessments included custom ASIC, FPGA, and DSP based architectures.
  • Study to identify future architectures of neural net products.
  • Resulted in concept for Crunch-860 product line an manufacture of 2000 products
  • Peace Shield Systems Lead analyst for modular, secure-voice/data equipment. Architecture consisted of loosely-coupled, multi-site, multi-processors (TMS320C25 DSP and Harris I/O processor (6303)). Modularity allows for small number of unique processor and peripheral modules configured into eight separate systems spanning secure-voice terminals, data and FAX terminals with small number of Line Replaceable Modules. Design comprehensive BITE system concept.
  • Developed System Architecture, Allocations, ICDs, Requirements
  • Completed FMA for Modules
  • SCOTT Communication Satellite - Senior software engineer for DSP algorithms design, high-level descriptions, ADA PDL documentation, C programming (HOL), and assembly code for TMS320C25 DSP. Perform code verification on TI TMS simulator tools in a VAX/VMS environment.
  • ALQ-131 VHSIC Transmit Control Asembly (VTCA) Lessons Learned for 1st successful VHSIC deployment.
  • Air Force ALQ-131 VTCA Subproject Manager, leading team of fifteen Work Package Managers and ASIC/FPGA hardware engineers for hardware/software design and CAE environment incorporating ten ASICs and VHSIC technologies into an electronic warfare pod.
  • 1st Successful VHSIC Program Integration and Delivery: Congress 1986.
  • Availability Improvements via higher MTBF, reduced MTTR using Maintenance And Diagnostic System (MADS™).
  • IR&D Principal Investigator for Maintenance and Diagnostic System™ to support generic VHSIC, ASIC, and off-the-shelf digital & analog technology BIST/BITE. Conceptual development and design of BIST ASIC to execute pseudo-random generation and signature-analysis techniques.
  • 1st TRW Insertion of MADS BITE, BIST, PRN techniques using integrated architecture.
  • IR&D Rules Expert on Advanced Avionics Availability Improvements program to develop real-time rule-based Expert diagnostic system to perform fault diagnosis and isolation to Line Replaceable Unit.
  • System analysis and architecture trades, algorithm development and simulation, hardware and software design code for Avionic speech recognition front-end employing the TMS32010 DSP and 68000. C-algorithm development on VAX/780 UNIX host for recursive and non-recursive filter-bank and Linear Predictive Coding techniques.
  • Voice Recognition algorithm designs, provided Texas Instruments support on hardware design of TMS32010 DSP. Design of C-based TMS32010 Simulator.
  • Design of Secure Voice terminal consisting of LPC Vocoder and 16-KBPS wire-line modem. 16KBPS QPSK Wire-line Modem system architecture and hardware design. Design incorporated custom AMD 29000 bit-slice architecture for real-time signal processing and Motorola 68K host embedded processor. Tightly coupled design with 29000 bit-slice executing high level macros.
  • Gained important project management skills and interpersonal skills motivating a team of ten engineers as a hardware project manager for new HF & UHF modem communications product lines. Develop requirements, design, build and code bit-slice array and control I/O processors satisfying throughput of real-time DSP techniques for LINK-11 (NAVY), TADIL-A, TAOC-85 modes.
  • Delivered HF modem product line using CMOS/SOS Intel bit-slice technology
  • Design analog/digital peripherals that will allow, in conjunction with processors, multitone (QPSK/Kineplex) and adaptive single tone HF in a multimode and simultaneous mode of operation. Modem features BITE subsystem.
  • NTDS PWA for parallel I/O and Custom Analog interfaces

R&D Engineer

GTE Sylvania
June 1975 to August 1978
Full-time
Needham
United States - California
  • First commercial design of 5-MHz, 40-bit wide horizontal instruction code 2900 bit-slice processor and microcode for multi-mode PSK satellite modem utilizing high-speed analog front end half-baud integration algorithm.
  • Met schedule and successful showing of product at Washington, DC Air Force show
  • Hardware lead engineer for Navy secure CVSD communications subsystem. Design and macro/assembly, and C program of BITE subsystem based on Z80.
Interests

Personal

  • Classical Grand Piano, Table Tennis (USTTA rating 1840), Darts, Billiards, Foosball.
  • US Citizen, Active US Passport
  • Agile Methods for Hardware Development
  • SECRET clearance (1980-1990, Status Inactive)
  • Willing to Travel & Relocate.
Resume created on DoYouBuzz
Download Download